The present invention relates to a semiconductor chip tray, and in particular, to semiconductor chip trays that are used in a state in which the semiconductor chip trays are stacked so as to overlap each other when housing, storing, and transporting semiconductor chips.
Semiconductor chip trays are used in a state of being stacked so as to overlap each other with semiconductor chips housed therein, in case that the semiconductor chip trays are packed and transported or that the semiconductor chip trays are transported along the process flow. In general, there is a need to make a substrate of a semiconductor chip thin. Accordingly, there is a need to reduce the warpage of a semiconductor chip tray. In particular, in the case of a liquid crystal display (LCD) driver integrated circuit (IC), a tendency for the length of a long side to increase becomes noticeable with an increase in the definition of a display panel. Accordingly, there is a stronger demand for reducing the warpage of the chip tray.
On the other hand, JP-A-2005-212797 discloses a technique for preventing the occurrence of chipping, tray scraping, and the like due to the corners of a semiconductor chip being in contact with the side walls of a chip pocket when the semiconductor chip is housed in the chip pocket of the chip tray (referred to as a tray pocket in JP-A-2005-212797). When chip pockets are formed by division using ribs arranged in a matrix, no rib is present in a portion that is in contact with the corner of a semiconductor chip.
JP-A-2001-035871 discloses a chip tray in which a through hole is provided on the bottom surface of a chip housing recess. In a step of forming a bump on the chip surface, the chip is adsorbed through the through hole.
JP-A-2010-040681 discloses a chip tray to prevent chipping or scratching of a semiconductor chip. A thin film made of a release material is formed on the chip tray surface including a recess that is a housing pocket to house a chip therein.